TY  - BOOK
AU  - Bhattacharya, Debashis
AU  - Hayes, John P.
TI  - HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING
SN  - 079239058X
U1  - 621.38173 
PY  - 1990///
CY  - Boston
PB  - Kluwer Academic Pub.
KW  - Very Large Scale Integration -- Testing
KW  - Integrated Circuits -- Very Large Scale Integration -- Computer Simulation
ER  -