TY  - BOOK
AU  - Radecka, Katarzyna
AU  - Zilic, Zeljko
TI  - Verification by error modeling: using testing techniques in hardware verification
SN  - 9781402076527
U1  - 621.395 
PY  - 2003///
CY  - Boston
PB  - Kluwer Academic Publishers
KW  - Integrated circuits
KW  - Very Large Scale Integration
KW  - Computer Aided design
ER  -