| 000 | 00719pam a2200241a 44500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 008 | 160408b1990 xxu||||| |||| 00| 0 eng d | ||
| 020 | _a0962748803 | ||
| 040 | _cIIT Kanpur | ||
| 041 | _aeng | ||
| 082 |
_a003 _bSt45d |
||
| 100 | _aSternheim, Eliezer | ||
| 245 | 1 |
_aDigital design with Verilog HDL _cEliezer Sternheim, Rajvir Singh and Yatin Trivedi |
|
| 260 |
_aCupertino, CA _bAutomata Publishing Com. _c1990 |
||
| 300 | _aviii, 214p | ||
| 440 | _aDesign Automation Series | ||
| 500 | _aFormerly Titled : Hardware Modeling With Verilog Hdl | ||
| 650 | _aHardware Discription Language | ||
| 650 | _aSystem Analysis | ||
| 700 | _aSingh, Rajvir | ||
| 700 | _aTrivedi, Yatin | ||
| 942 | _cBK | ||
| 999 |
_c325881 _d325881 |
||