000			00740pam a2200205a 44500
008			160408b2003 xxu||||| |||| 00| 0 eng d
020			_a9781402076527
040			_aP K Kelkar Library, IIT Kanpur
082			_a621.395 _bR117v
100			_aRadecka, Katarzyna
245	0		_aVerification by error modeling _busing testing techniques in hardware verification _cKatarzyna Radecka and Zeljko Zilic
260			_aBoston _bKluwer Academic Publishers _c2003
300			_axiv, 216p
440			_aFrontiers In Electronics Testing / Edited By Vishwani D. Agrawal _v
650			_aIntegrated circuits
650			_aVery Large Scale Integration
650			_aComputer Aided design
700			_aZilic, Zeljko
997			_aA174930 s C
999			_c371608 _d371608