000			01785 a2200205 4500
003			OSt
020			_a9781108494540
040			_cIIT Kanpur
041			_aeng
082			_a621.3815364 _bR219d
100			_aRazavi, Behzad
245			_aDesign of CMOS phase-locked loops _bfrom circuit level to architecture level _cBehzad Razavi
260			_bCambridge University Press _c2020 _aCambridge
300			_axvi, 492p
520			_aUsing a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.
650			_aPhase-locked loops -- Design and construction
650			_aMetal oxide semiconductors, Complementary -- Design and construction
650			_aOscillators, Electric -- Design and construction
942			_cBK _01
999			_c565336 _d565336