Image from Amazon.com
Verification techniques for system-level design
Material type:
TextSeries: The Morgan Kaufmann Series In Systems On Silicon ; Publication details: Amsterdam Elsevier 2008Description: viii, 240pISBN: - 9780123706164
- 621.3815 F955v
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | |
|---|---|---|---|---|---|---|---|---|
Books
|
PK Kelkar Library, IIT Kanpur | General Stacks | 621.3815 F955v (Browse shelf(Opens below)) | Available | A160090 |
Total holds: 0
Browsing PK Kelkar Library, IIT Kanpur shelves, Collection: General Stacks Close shelf browser (Hides shelf browser)
| No cover image available |
|
|
|
No cover image available |
|
|
||
| 621.3815 F556t TRANSISTOR CIRCUIT ANALYSIS AND DESIGN | 621.3815 F582a Analog design and simulation using OrCAD capture and PSpice | 621.3815 F811c Creating Asseration-Based IP | 621.3815 F955v Verification techniques for system-level design | 621.3815 G181L LABORATORY MANUAL ON DIGITAL DESIGN USING | 621.3815 G341c CMOS capacitive sensors for lab-on-chip applications | 621.3815 G755c Carbon nanotube-polymer composites |
There are no comments on this title.
Log in to your account to post a comment.