Welcome to P K Kelkar Library, Online Public Access Catalogue (OPAC)

Amazon cover image
Image from Amazon.com

Design of CMOS phase-locked loops : from circuit level to architecture level

By: Language: English Publication details: Cambridge University Press 2020 CambridgeDescription: xvi, 492pISBN:
  • 9781108494540
Subject(s): DDC classification:
  • 621.3815364 R219d
Summary: Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.
List(s) this item appears in: New arrival May 09 to 15, 2022
Star ratings
    Average rating: 5.0 (1 votes)
Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
Books Books PK Kelkar Library, IIT Kanpur General Stacks 621.3815364 R219d (Browse shelf(Opens below)) Checked out to Himanshu Vyas (S23104060900) 12/07/2025 A185703
Total holds: 0

Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.

There are no comments on this title.

to post a comment.

Powered by Koha