Design of CMOS phase-locked loops : from circuit level to architecture level
Language: English Publication details: Cambridge University Press 2020 CambridgeDescription: xvi, 492pISBN:- 9781108494540
- 621.3815364 R219d
Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | |
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PK Kelkar Library, IIT Kanpur | General Stacks | 621.3815364 R219d (Browse shelf(Opens below)) | Checked out to Himanshu Vyas (S23104060900) | 12/07/2025 | A185703 |
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621.3815364 Eg13p2 Phase-lock basics | 621.3815364 G171P3 PHASELOCK TECHNIQUES | 621.3815364 G569P PHASE-LOCKED LOOP ENGINEERING HANDBOOK FOR INTEGRATED CIRCUITS | 621.3815364 R219d Design of CMOS phase-locked loops from circuit level to architecture level | 621.3815365 K189p Pulse-width modulated DC-DC power converters | 621.381537 AL55P DIGITAL PROTECTION OF POWER APPARATUS AND SYSTEMS | 621.381537 C734d DIGITAL LOGIC AND STATE MACHINE DESIGN |
Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.
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